Things are a little weird as I suggested in my previous post.
I have the CF card installed and if I use the ROM monitor in the Interak to access it through a series of Port commands, I can see what appears to be sensible data. If, however I use a piece of Z80 assembly language, I never see the CF card become ready.
I have tried my own code and two other variants found on the web.
Let me show you what I mean. This snippet came from Scott Baker’s website…
1069: WAITDRQ: 1069: F5 PUSH AF 106A: WAITDRQLP: 106A: DB67 in A,(I7) 106C: E608 AND 08H 106E: FE08 cp 08H 1070: 20F8 JR NZ, WAITDRQLP 1072: F1 POP AF 1073: C9 RET
To use this, I have set up the sector and all other parameters needed for a disk read. If I run this routine, it never finishes. breaking the code at 0x106C shows that the accumulator is either 0x40 or 0x41. Which means “Drive ready” or “Drive ready + error”.
However, if I use “P 67” at the monitor, I get “0x58” which means “Drive ready + Drive seek complete + Data request ready”.
I can run from 0x106A to 106C again and again I see 0x40 or 0x41 in the accumulator. If I use “P67” again, again I see 0x58.
Can anyone see the deliberate mistake because I can’t 🙁
Maybe you need a short delay between each register-setup write? Some controllers are funny like that. Also, what does the OR 0xE0 in the last register write setup do?